Solar Charger Constant Voltage PPT

I decided to charge some of my Li-Ion-batteries with a solar panel. With 50Wh maximum capacity and a super idealistic charging time of 2h a panel of 20W is the absolute minimum. During winter only 10% of this power is left, thus 2W of charging power in average (less hours of sunshine and lower angle). It'll need >2 days to charge the battery. But for a first test run it is sufficient. The specs summed up:

The battery is rather unspecific, except the upper limit of 3 cells in series. With a peak voltage of 4.2V there's a margin of only 17-12.6V=4.4V from the optimum power point. And here we are in the middle of the discussion. Many methods exist to find the optimum power point for a solar panel. I decided to use the constant voltage method. A small panel doesn't provide enough power for tough computing. I cannot afford 30mA or more for a floating point unit providing an incremental conductance algorithm. Also perturb and observe, less complex than the previous but still with multiplications is not an option. Being 2-3% off doesn't mean that much with a panel less than or equal to 100W. There are 8% loss because of vertical misalignment and up to 20% because of horizontal – a way more attractive efficiency target. With perturb and observe it is certain, to not hit the sweet spot but to move around it permanently with hard to estimate losses.

Constant voltage is simple enough: open circuit voltage is proportional to the maximum power point voltage. All I need to do is find the UMPP. For my panel it is in the datasheet: 17.6V at 25°C. To add a little bit of complexity I decided to use Li-Ion-batteries. Thus I need to design maximum power point tracking and charging. Luckily I came accross an integrated circuit from Texas Instruments: BQ24650. It is a synchronous buck controller with constant voltage MPPT to charge Li-Ion-cells. It is not cheap, 5€ with additional components. But: I'd also need the components for a discrete or microcontroller driven solution. The IC is very sensitive, a shunt resistor of 20mΩ is absolutely sufficient. In addition the IC needs a voltage divider on the panel to measure the input voltage. A total resistance of 600kΩ is absolutely sufficient. So the losses are very low, even though synchronous buck conversion wouldn't be necessary with 12V average output voltage.

The circuit is a 90% copy from the datasheet and an application note. I added special dividers to avoid strange E96 resistors and stick with E24 series. Two resistors in series are easier to place then two in parallel – more gaps to route through. An ESD protection diode (D3) at the input as well a diode in series (D2) to prevent reverse polarity are optional. I also added the chip enable trick by pulling down the MPPSET pin. Thermal measurement is for a standard A103 NTC (10k @ 25°C, beta of 3800).

The MOSFETs are the same as on the evaluation board from texas instruments. They provide tight thermal coupling because of the Power SO-8 package and have a quite low RDSon. With a low gate capacity switching losses are minimal. Due to the bootstrap circuitry in the IC both MOSFETs can be NMOS. The dual NMOS type needs very little space compared to the power that could pass. This means short traces. A TO-220 or similar SMD package would need twice the amount of space. If the full 10A charging current is not needed, any other SO-8 provided NMOS-pair would do, as long as the pins have the same order, e.g. some IRF-types from Vishay have the same pin ordering.